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SiFive
Senior RTL Design Engineer - CPU Frontend
Cambridge On-site 2-5 yrs exp Semiconductor Manufacturing 532 employees
CPU RTL DesignRISC-VChiselVerilogSystemVerilog
Requirements
Requires a bachelor’s or master’s degree in computer science, computer engineering, electrical engineering, or a related field, or equivalent experience, plus at least three years of design experience. Candidates need CPU RTL design experience in relevant frontend or cache areas, proficiency in Verilog, SystemVerilog, or VHDL, and strong software engineering skills; Scala/Chisel, RISC-V, and verification knowledge are advantageous.
Job Description
About SiFive
As the pioneers who introduced RISC-V to the world, SiFive is transforming the future of compute by bringing the limitless potential of RISC-V to the highest performance and most data-intensive applications in the world. SiFive’s unrivaled compute platforms are continuing to enable leading technology companies around the world to innovate, optimize and deliver the most advanced solutions of tomorrow across every market segment of chip design, including artificial intelligence, machine learning, automotive, data center, mobile, and consumer. With SiFive, the future of RISC-V has no limits.
At SiFive, we are always excited to connect with talented individuals, who are just as passionate about driving innovation and changing the world as we are.
Our constant innovation and ongoing success is down to our amazing teams of incredibly talented people, who collaborate and support each other to come up with truly groundbreaking ideas and solutions. Solutions that will have a huge impact on people's lives; making the world a better place, one processor at a time.
Are you ready?
To learn more about SiFive’s phenomenal success and to see why we have won the GSA’s prestigious Most Respected Private Company Award (for the fourth time!), check out our website and Glassdoor pages.
Job Description:
Responsibilities
This position requires a successful background and reference checks and satisfactory proof of your right to work in:
United Kingdom
Any offer of employment for this position is also contingent on the Company verifying that you are a authorized for access to export-controlled technology under applicable export control laws or, if you are not already authorized, our ability to successfully obtain any necessary export license(s) or other approvals.
SiFive is an equal opportunity employer. We celebrate diversity and are committed to creating an inclusive environment for all employees.
As the pioneers who introduced RISC-V to the world, SiFive is transforming the future of compute by bringing the limitless potential of RISC-V to the highest performance and most data-intensive applications in the world. SiFive’s unrivaled compute platforms are continuing to enable leading technology companies around the world to innovate, optimize and deliver the most advanced solutions of tomorrow across every market segment of chip design, including artificial intelligence, machine learning, automotive, data center, mobile, and consumer. With SiFive, the future of RISC-V has no limits.
At SiFive, we are always excited to connect with talented individuals, who are just as passionate about driving innovation and changing the world as we are.
Our constant innovation and ongoing success is down to our amazing teams of incredibly talented people, who collaborate and support each other to come up with truly groundbreaking ideas and solutions. Solutions that will have a huge impact on people's lives; making the world a better place, one processor at a time.
Are you ready?
To learn more about SiFive’s phenomenal success and to see why we have won the GSA’s prestigious Most Respected Private Company Award (for the fourth time!), check out our website and Glassdoor pages.
Job Description:
Responsibilities
- Architect, design and implement new features, performance improvements, and ISA extensions in RISC-V CPU core generators using Chisel.
- Integrate new design content into SiFive’s Chisel/FIRRTL framework and contribute to improvements to that framework to enable automatic configuration/generation of documentation, verification testbenches and tests, and packaged software.
- Perform initial sandbox verification, and work with the design verification team to create and execute thorough verification test plans.
- Work with the physical implementation team to implement and optimize physical design to meet frequency, area, and power goals.
- Collaborate with the performance modeling team for performance exploration and optimization to meet performance goals.
- Microarchitecture development and specification. Ensure that knowledge is shared via great documentation and participation in a culture of collaborative design.
- BS/MS degree in computer science, computer engineering, electrical engineering or related field, or equivalent experience.
- 3+ years of design experience.
- Academic or professional experience with CPU RTL design in one or more of the following areas: instruction fetch, instruction decode, branch prediction, coherent caches, cache prefetching, TLBs.
- Proficiency in hardware (RTL) design in Verilog, System Verilog, or VHDL.
- Strong software engineering skills/background, including:
- Object-oriented, aspect-oriented, and particularly functional programming
- Templated metaprogramming, in any language
- Compiler infrastructures, particularly for domain-specific languages
- Data modeling, particularly intermediate representations for optimizing or transforming compiler passes
- Test-driven development, particularly ability to write adaptive unit tests
- Attention to detail and a focus on high-quality design.
- Ability to work well with others and share the belief that engineering is teamwork.
- Experience with Scala/Chisel, Bluespec, or some other language/DSL for expressing configurable hardware via software.
- Knowledge of RISC-V architecture.
- Expertise in CPU processor designs in one or more of the following areas is a plus: instruction fetch; instruction decode; register renaming and instruction scheduling; vector units; load-store unit.
- Knowledge of verification principles, testbenches, UVM, and coverage.
- Experience with Git/Github, Jira, Confluence.
This position requires a successful background and reference checks and satisfactory proof of your right to work in:
United Kingdom
Any offer of employment for this position is also contingent on the Company verifying that you are a authorized for access to export-controlled technology under applicable export control laws or, if you are not already authorized, our ability to successfully obtain any necessary export license(s) or other approvals.
SiFive is an equal opportunity employer. We celebrate diversity and are committed to creating an inclusive environment for all employees.
Education
Bachelor DegreePostgraduate Degree
Skills
CPU RTL DesignRISC-VChiselVerilogSystemVerilogVHDLMicroarchitectureInstruction FetchInstruction DecodeBranch PredictionCoherent CachesCache PrefetchingTLBsFunctional ProgrammingCompiler InfrastructureVerification
About SiFive
The heart of SiFive is RISC-V! SiFive creates the building blocks of RISC-V-based IP that are the inevitable innovative reimagining of every computing platform.
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