Senior DFT Engineer

In this role, you will be responsible for creating, implementing, and verifying DFT solutions for future ASIC designs, ensuring that quality standards are upheld for products shipping in volume. You will leverage advanced DFT methodologies to optimize test coverage, cost, and time-to-market. This position is office based in Cambridge and visa can be considered for exceptional candidates only!

Responsibilities:

• Define and implement DFT strategies at the chip, subsystem, and IP levels, balancing structural and functional methods while making pragmatic trade-offs
• Utilize Tessent DFT tool flows for inserting MBIST, EDT, SSN, scan controls via IJTAG, and IP test using ICL/PDL in both flat and hierarchical designs
• Verify DFT structures and debug related issues to ensure robust design implementation
• Support DFT processes through implementation and sign-off, including generating timing constraints and resolving timing, power, and formal equivalence issues

Qualifications:

• A degree in electronic engineering, computer science, or a related discipline plus at least 5 years industry experience in DFT Engineering
• Proven experience with IC development flows
• Proficiency with Tessent DFT tools
• Strong understanding of complex IP issues related to DFT, including on-chip clocking
• Hands-on experience in ATPG, MBIST, and simulation debugging, including UPF-related issues
• Proficiency in scripting, particularly TCL

If you are a dedicated professional with a passion for DFT engineering and a desire to contribute to cutting-edge ASIC development and want to know more about this opportunity, please contact Ane @ IC Resources with your CV and a time for an initial call.

Priority will be given to application from within the UK followed by EU.