Staff / Senior Staff PMIC Design Engineer

Insight Global are seeking a Staff Engineer, Analogue PMIC Design for a leading semiconductor and consumer technology organisation focused on delivering high‑performance, low‑power SoC solutions.

This is a permanent opportunity based in Cambridge, England, operating within a collaborative ASIC engineering environment.

This role is offering a relocation assistance and sponsorship if needed.

As a senior individual contributor, this role takes end‑to‑end ownership of analogue power management IP, partnering closely with system architects, digital design, and verification teams to deliver fully validated PMIC blocks for large‑scale consumer and mobile SoCs. The position focuses on solving complex analogue challenges under tight power, performance, and area constraints.

Key Responsibilities

• Define architecture for complex power‑management blocks and lead development from concept through tape‑out
• Own analogue circuit design, simulation, verification, and technical documentation
• Deliver fully verified power management IP blocks for integration into SoCs
• Collaborate with digital, verification, and system teams to ensure design robustness across all process, voltage, and temperature corners
• Support verification and, where required, subsystem‑level validation activities
• Act as a technical expert in analogue sub‑cell and subsystem design
• Ensure design quality and timely delivery in coordination with macro and project leads

Must‑Have Requirements Include:

• Bachelor’s, Master’s, or PhD in Science, Engineering, or a related field
• Strong background in analogue or mixed‑signal IC design
• Hands‑on ownership of PMIC or power‑related IP blocks
• Experience using Cadence and Mentor analogue design and verification tools
• Proven delivery of fully verified analogue blocks through tape‑out
• Background in low‑power consumer or mobile SoC environments

Plusses Include:

• Experience supporting silicon bring‑up or validation teams
• Design experience with key power management IP such as SMPS and LDOs
• Exposure to additional power blocks including bandgaps, references, charge pumps, or clock generators
• Experience with automotive or high‑reliability power designs
• Understanding of low‑power, system‑level architectural trade‑offs
• Familiarity with CMOS process technologies